In the manufacture of integrated circuits, copper interconnects are generally formed on a semiconductor substrate using a copper dual damascene process. Such a process begins with a trench being etched into a dielectric layer and filled with a barrier layer, an adhesion layer, and a seed layer. A sputtering process may be used to deposit a tantalum nitride (TaN) barrier layer and a tantalum (Ta) or ruthenium (Ru) adhesion layer (i.e., a TaN/Ta or TaN/Ru stack) into the trench. The TaN barrier layer prevents copper from diffusing into the underlying dielectric layer. The Ta/Ru adhesion layer enables subsequently deposited metals to nucleate on the TaN barrier layer. This may be followed by a sputtering process to deposit a copper seed layer into the trench and an electroplating process to fill the trench with copper metal.
As device dimensions scale down, the trench becomes more narrow, thereby causing the aspect ratio of the trench to become more aggressive. This gives rise to issues such as trench overhang during the two copper deposition processes. Trench overhang eventually causes the trench opening to become pinched-off, resulting in inadequate gapfill and void formation. Additionally, as trenches decrease in size, the ratio of barrier metal to copper in the overall interconnect structure increases, thereby increasing the electrical line resistance and RC delay of the interconnect.
One approach to addressing these issues is to reduce the thickness of the TaN/Ta or TaN/Ru stack, for instance, by replacing the stack with a noble metal layer. This widens the available gap for subsequent metallization and increases the final copper volume fraction. Unfortunately, voids may still form when using current interconnect fabrication procedures with noble metal barrier/adhesion layers.